So-called clock signals are used in semi-conductor components, in particular in memory components such as DRAMs (DRAM=Dynamic Random Access Memory and/or Dynamic Read/Write Memory)—for instance based on CMOS technology—for the chronological co-ordination of the processing and/or relaying of data.
In conventional semi-conductor components a single clock signal (i.e. a so-called single-ended clock signal)—present on a single line—is generally applied.
The data can then for instance be relayed during the ascending clock flank of the single-ended clock signal (or alternatively for instance in each case during the descending single-ended clock flank).
In conventional technology in addition, so-called DDR components, in particular DDR-DRAMS (DDR-DRAM=Double Data Rate DRAMs and/or DRAMs with double data rate), are already known.
With DDR components two differential, conversely equal clock signals—present on two separate lines—are used instead of a single clock signal (“single-ended” clock signal) present on a single line.
Whenever for instance the first of the two clock signals changes its state from “high logic” (for instance from a high voltage level) to “low logic” (for instance to a low voltage level) the second clock signal—essentially simultaneously—changes its state from “low logic” to “high logic” (for instance from a low to a high voltage level).
Conversely, whenever for instance the first clock signal changes its state from “low logic” (for instance from a low voltage level) to “high logic” (for instance to a high voltage level) the second clock signal—again essentially simultaneously—changes its state from a “high logic” to “low logic” (for instance from a high to a low voltage level). In DDR components data is usually relayed during both the ascending flank of the first clock signal as well as during the ascending flank of the second clock signal (and/or during the descending flank of the first clock signal as well as during the descending flank of the second clock signal).
This has the effect that in a DDR component the relaying of data takes place more frequently and/or more quickly (in particular twice as frequently or twice as quickly) than with corresponding conventional components with a single and/or “single-ended” clock signal, i.e. the data rate is higher, in particular twice as high as that of corresponding conventional components.
DDR components comprise for instance two—external—clock connections at which corresponding differential clock signals clk, bclk—generated by an external clock generator—can be applied and relayed—directly—to corresponding inputs of a clock receiver circuit device.
Conventional clock receiver circuit devices for instance comprise four transistors, for instance a first and a second p-channel field effect transistor (for instance two p-channel MOSFETs) as well as a first and a second n-channel field effect transistor (for instance two n-channel MOSFETs).
The source of the first n-channel field effect transistor can be connected with a (DC or constant) current source—connected with the ground potential—via corresponding lines. In similar fashion the source of the second n-channel field effect transistor can be connected via corresponding lines with the (DC) current source—connected with the ground potential.
In addition, the gate of the first n-channel field effect transistor of the clock receiver circuit device can for instance be connected with the above (first) input of the circuit (at which for instance the above—first—clock signal clk is present) and the gate of the second n-channel field effect transistor for instance with the above (second) input of the circuit (at which for instance the above second clock signal bclk, inverted in relation to the first clock signal clk, is present).
The drain of the first n-channel field effect transistor can be connected with the gate of the first and second p-channel field effect transistor via a corresponding line, and with the drain of the first p-channel field effect transistor, as well as—via a corresponding line—with a (first) output of the clock receiver circuit (at which a (first) output signal bout can be detected).
In corresponding fashion the drain of the second p-channel field effect transistor can be connected with the drain of the second p-channel field effect transistor, as well as—via a corresponding further line—with a (second) output of the clock receiver circuit (at which a (second) output signal out can be detected).
The source of the first and second p-channel field effect transistor can in each case be connected with the corresponding supply voltage vddq.
The first output signal bout emitted by the clock receiver circuit device corresponds with the signal bclk present at the (second) input of the clock receiver circuit device, and the second output signal out, emitted by the clock receiver circuit device, with the signal clk present at the (first) input of the clock receiver circuit device (whereby—depending on the nature of the change of the input signals clk and/or bclk (for instance from “high logic” to “low logic”, or vice versa)—the delay periods caused by the clock receiver circuit device can differ relatively strongly).
The output signals out, bout emitted by the clock receiver circuit device can be relayed to further circuits provided in the semi-conductor component, where they can for instance be used for the chronological co-ordination of the processing and/or relaying of data, i.e. as differential clock signals out, bout.